Yamaha CD-S2100 Manual De Instrucciones página 15

■ Setting the DPLL (Digital Phased Lock
Loop) bandwidth
The audio DAC (ES9016) of this unit employs DPLL to
generate accurate clock signals synchronized with the
clock of the input digital audio signal. The 7-step DPLL
bandwidth setting gives the unit tolerance for fluctuation
of the clock of the input digital signal and adjustment of
the accuracy of the operating clock in the DAC.
1
Press SOURCE to select the audio source to
be played back.
The DPLL bandwidth can be set for each audio
source, respectively.
2
Within 5 seconds after selecting the audio
source, press ENTER.
The unit enters the setting mode, and the DPLL
bandwidth currently set appears on the information
display.
3
Select the DPLL bandwidth using the
(pause) key and the
Each time the (pause) key is pressed, the
bandwidth changes in the following order. If you
press the (stop) key, it changes in reverse order.
Lowest
Low
Med-Low
Medium
Med-Hi
High
Highest
(stop) key.
(default)
4
Press ENTER.
The setting value flashes for 3 seconds, then the unit
resumes to normal mode.
To cancel the setting, press CLEAR.
Notes
• As the DPLL bandwidth setting value approaches "Lowest," the
accuracy of the operating clock in the DAC improves, but the
unit may be susceptible to a change in the clock of the external
component. The sound from such a component may more easily
skips.
• As the DPLL bandwidth setting value approaches "Highest,"
the accuracy of the operating clock in the DAC deteriorates, but
the unit is far less susceptible to a change in the clock of the
external component, and the sound from such a component
hardly skips.
15
En