Pcb Principal; Cpu - Brother HL-5130 Manual De Servicios

1.3

PCB principal

Para el diagrama del circuito completo de la PCB principal, vea el
"Diagrama del circuito de la PCB principal"
1.3.1

CPU

El CPU RISC de 32bit de Fujitsu SPARClite está construído en el ASIC. Mientras el CPU es
controlado con una frecuencia de reloj de 66.66 MHz en el bloque lógico, este corre a 133.33
MHz, que es multiplicando el reloj de la fuente por dos
<HL-5130/5140/5150D>
TP731
DATA[0]
DATA[1]
DATA[2]
DATA[3]
TP732
DATA[4]
DATA[5]
DATA[6]
DATA[7]
TP733
DATA[8]
DATA[9]
DATA[10]
DATA[11]
TP734
DATA[12]
DATA[13]
DATA[14]
DATA[15]
DATA[15-0]
7F/8F/3-6A
C52
C100
AT-49 66.6666MHz
C57
0V
C2
C60
0V
C103
U5
TP6
40
22
RA12
DATA00 ADR01/24
1 8
41
DATA01 ADR02
2 7
42
DATA02 ADR03
3 6
43
DATA03 ADR04
4 5
TP7
44
RA13 22
DATA04 ADR05
1 8
45
DATA05 ADR06
2 7
46
DATA06 ADR07
3 6
47
DATA07 ADR08
4 5 TP8
48
RA15 22
DATA08 ADR09
1 8
49
DATA09 ADR10
2 7
53
DATA10 ADR11
3 6
54
DATA11 ADR12
4 5 TP9
55
RA14 22
DATA12 ADR13
1 8
56
DATA13 ADR14
2 7
57
DATA14 ADR15/BA0
3 6
58
DATA15 ADR16/BA1
4 5
59
DATA16/IO ADR17/RASN
60
DATA17/IO ADR18/CASN
61
DATA18/IO ADR19/WEN
62
DATA19/IO ADR20/DQM0
63
DATA20/IO ADR21/DQM1
64
DATA21/IO ADR22/DQM2
67
DATA22/IO ADR23/DQM3
68
DATA23/IO
69
DATA24/IO
70
DATA25/IO ROMCSN0
71
DATA26/IO ROMCSN1
72
DATA27/IO
73
DATA28/IO IOWEN
74
DATA29/IO IORDN
75
0V DATA30/IO
76
TP736 DATA31/IO
SDCLK0
SDCLK1
196
EXINTN0 SDCLK2
VDD3
SDCKE0
C43
TP5
216
0V RSTN SDCKE1
C101
SDCSN0
TP705
R70 87
SCKOUT SDCSN1
1
0
SDCSN2
R71
X2 1M
85
2
SCKIN SDSDA
SDSCL
TP1009
L6
Aurora
0.82uH
Fig. 0-3
3
HL-5130/5140/5150D/5170DN MANUAL DE SERVICIOS
SUPLEMENTO 1 a 7.
en este manual.
VDD3
TP35 TP198
9
R90 33
10
RA8 10
4 5
11
3 6
12
2 7
TP36
13
1 8
14
RA9 10
4 5
15
3 6
16
2 7
TP37
17
1 8
18
RA10 10
4 5
19
3 6
25
2 7
TP726
26
1 8
27
10
RA11
4 5
28
3 6
29
2 7
TP727
30
1 8
TP1000
31
R97
10
TP1001
32
R98 10
TP1002
33
R91
22
TP728
34
R92
33
TP729
35
R93 33
TP730
36
R94 33
TP10 TP700
211 R56
33
ROMCSN0
6D/8D
212
TP351
TP12 TP702
213 R49
33
IOWEN
TP13 TP703
6D
214 R51
33
IORDN
6D/8D
0V
TP14 TP196
95 R63
51
SDCLK0
TP15
8B
94 R65
0
SDCLK1
TP16
3-4C
93 R68
0
SDCLK2
3-4C
TP17 TP1003
R57
96
51
TP26
R61
97
0
R62
TP29 TP197
R42
90
51 R58
SDCSN0
TP30
89 R41 8A
33
SDCSN1
TP31
88 R50 3-2D
33
SDCSN2
R53
3-2D
VDD3
TP32 4.7k
92 R52
33
TP33
91 R48 3-2C
33
3-2C
ADR[1]
ADR[2]
ADR[3]
ADR[4]
ADR[5]
ADR[6]
ADR[7]
ADR[8]
ADR[9]
ADR[10]
ADR[11]
ADR[12]
ADR[13]
ADR[14]
ADR[15]
ADR[16]
ADR[17]
ADR[18]
ADR[19]
ADR[20]
ADR[21]
ADR[22]
ADR[23]
SDCKE0
8B
SDCKE1
3-4C
4.7k
4.7k
0V
SDSDA
SDSCL
ADR[23-1]
6F/7C/7F/3-2E/
3-4D/3-4C/8A/
8B/3-2D