Fujitsu SPARC Enterprise T5120 Manual De Servicio página 61

4. Cambie a la consola del sistema para ver el resultado de POST:
sc> console
El
EJEMPLO DE CÓDIGO 2-5
EJEMPLO DE CÓDIGO 2-5
sc> console
Enter #. to return to ALOM.
2007-07-03 10:25:12.081 0:0:0>@(#)SPARC Enterprise POST
4.x.build_119***PROTOTYPE BUILD*** 2007/06/06 09:48
/export/delivery/delivery/4.x/4.x.build_119/post4.x/Niagara/huro
n/integrated (root)
2007-07-03 10:25:12.550 0:0:0>VBSC cmp0 arg is: 00ff00ff.ffffffff
2007-07-03 10:25:12.653 0:0:0>POST enabling threads:
00ff00ff.ffffffff
2007-07-03 10:25:12.766 0:0:0>VBSC mode is: 00000000.00000001
2007-07-03 10:25:12.867 0:0:0>VBSC level is: 00000000.00000001
2007-07-03 10:25:12.966 0:0:0>VBSC selecting POST MAX Testing.
2007-07-03 10:25:13.066 0:0:0>VBSC setting verbosity level 3
2007-07-03 10:25:13.161 0:0:0>Niagara2, Version 2.1
2007-07-03 10:25:13.247 0:0:0>Serial Number: 0fac006b.0e654482
2007-07-03 10:25:13.353 0:0:0>Basic Memory Tests.....
2007-07-03 10:25:13.456 0:0:0>Begin: Branch Sanity Check
2007-07-03 10:25:13.569 0:0:0>End
2007-07-03 10:25:13.668 0:0:0>Begin: DRAM Memory BIST
2007-07-03 10:25:13.793
0:0:0>..........................................................
......................................
2007-07-03 10:25:38.399 0:0:0>End
2007-07-03 10:25:39.547 0:0:0>Sys 166 MHz, CPU 1166 MHz, Mem 332
MHz
2007-07-03 10:25:39.658 0:0:0>L2 Bank EFuse = 00000000.000000ff
2007-07-03 10:25:39.760 0:0:0>L2 Bank EFuse = 00000000.000000ff
2007-07-03 10:25:39.864 0:0:0>Core available Efuse =
ffff00ff.ffffffff
2007-07-03 10:25:39.982 0:0:0>Test Memory.....
2007-07-03 10:25:40.070 0:0:0>Begin: Probe and Setup Memory
2007-07-03 10:25:40.181 0:0:0>INFO:
...
2007-07-03 10:29:21.683 0:0:0>INFO:
2007-07-03 10:29:21.686 0:0:0>POST Passed all devices.
2007-07-03 10:29:21.692 0:0:0>POST:Return to VBSC.
ilustra el resultado resumido de POST:
Resultado de POST (resumido)
: Branch Sanity Check
: DRAM Memory BIST
Capítulo 2 Diagnósticos del servidor
4096MB at Memory Branch 0
2-29