Ssi Interface; Principle - Balluff BML Información Básica

Interfaces for BML Magnetic Encoder System
2
Interfaces (continued)
2.2

SSI interface

RS422 differential signal
If the sensor is supplied with voltage that is
isolated from the processing electronics, the
GND for this voltage must be connected to the
GND of the processing electronics.
Suggested circuit for processing:
+Clk
–Clk
+Data
–Data
GND
U
Sensor
B
Fig. 2-1: Wiring example for a sensor with controller
The wires for Clk, Data and Power must be in
twisted pairs (see Fig. 2-1).
Clock pulses may only be sent when there is power to the
measuring system.
The data output of the sensor must be loaded
with 120 Ω, otherwise incorrect measurements
may result.
Trigger time
Clk
Data
Bit n-1
t1
T
Clk
Clk
t
v
Data
T
A
Clk
+Clk Burst
Data Clock burst
Fig. 2-2: Signals with SSI interface
Bit n-1 Bit n–2 ... Bit 1
0 0
0 0
0 0
Tab. 2-2: Value of the sent bits for binary transmission
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Clk
Data
120Ω
Controller
Bit n–2 Bit n–3 ...
t
v
Bit 0 Dec value
0 1 1
1 0 2
1 1 3
2.2.1

Principle

SSI stands for Synchronous Serial Interface and describes
a digital synchronous interface with a differential clock line
and a differential data line.
With the first falling clock edge (trigger time), the data
word to be output is buffered in the sensor head. Data
output takes place with the first rising clock edge, i.e. the
sensor supplies a bit to the data line for each rising clock
edge. In doing so, the line capacities and delays of drivers
t when querying the data bits must be taken into account
v
in the controller.
The max. clock frequency f
length. The t time, also called monoflop time, is started
m
with the last falling edge and is output as the low level with
the last rising edge. The data line remains at low until the
t time has elapsed. Afterwards, the sensor is ready again
m
to receive the next clock packet.
The meaning of the bits and relationship
between maximum cable length and clock rate
is described in the guide for the sensor.
t m
... Bit 0
t2
T = 1/f SSI clock period, SSI clock frequency
Clk Clk
T = 1/f Sampling period, sampling rate
A A
n Number of bits to be transmitted
(requires n+1 clock impulses)
t = 2 × T Time until the SSI interface is ready
m Clk
again
t = 150 ns Transmission delay times (measured
v
with a 1 m cable)
depends on the cable
Clk
t
t
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