Tabla de contenido
Descripción de Circuitos
No
Pin Name
211
ADDR9
212
Vddo
213
ADDR10
214
Vsso
215
ADDR11
216
ADDR12
217
ADDR13
218
ADDR14
219
Vsso
220
ADDR15/CTOut[0]
221
ADDR16/CTOut[1]
222
ADDR17/CTOut[2]
223
ADDR18/CTOut[3]
224
Vsso
225
ADDR19/CTOut[4]
226
ADDR20/CTOut[5]
227
ADDR21/CTOut[6]
228
ADDR22/CTOut[7]
229
Vddo
230
ADDR23/PTOut
231
Vsso
232
TESTSE
233
TM
234
Vddi
235
MCLK
236
Vssi
237
FILTER
238
CPUTEST
239
nRESET
240
nRSTOUT
5-10
I/O
Reset Value
O
L
Vdd
-
O
L
Vss
-
O
L
O
"
O
"
O
"
Vss
-
O
L
O
"
O
"
O
"
Vss
-
O
L
O
"
O
"
O
"
Vdd
-
O
L
Vss
-
I
-
I
-
Vcca
-
I
-
Vssa
-
O
-
I
-
I
-
O
L
Augosto 2001
Description
Address Bus 9 for ROM
5 V
Address Bus 10 for ROM
5 V Gnd
Address Bus 11 for ROM
Address Bus 12 for ROM
Address Bus 13 for ROM
Address Bus 14 for ROM
5 V Gnd
Address Bus 15 for ROM
Address Bus 16 for ROM
Address Bus 17 for ROM
Address Bus 18 for ROM
5 V Gnd
Address Bus 19 for ROM
Address Bus 20 for ROM
Address Bus 21 for ROM
Address Bus 22 for ROM
5 V
Address Bus 23 for ROM
5 V Gnd
Scan Enable :Tied to Gnd
Test Mode :Tied to Gnd
3.3 V
Master Clock
3.3 V Gnd
Charge Pump Out :
Capacitor is connected
CPU Test Mode :
Tied to Gnd
Reset Input
Reset Output
Versión de Lanzamiento
PAD
PHOB8, 8 mA
PHOB8, 8 mA
PHOB8, 8 mA
"
"
"
PHOB8, 8 mA
"
"
"
PHOB8, 8 mA
"
"
"
PHOB8, 8 mA
PHILD50, ST
"
for PLL
PHIC
for PLL
POBA
PHILD50, ST
PHIL, ST
PHOB8, 8 mA
WorkCentre Pro 412
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