7.5.1
Bits de Control y Estado ......................................................................................................... 55
7.5.2
7.5.3
7.5.4
7.5.5
7.6
7.6.1
Bits de Control y Estado ......................................................................................................... 57
7.6.2
7.6.3
7.6.4
7.6.5
8
8.1
8.2
8.3
OPERACIÓN DEL MAESTRO ......................................................................................................... 60
8.4
8.4.1
9
9.1
9.2
10
A134/F34 - BUS OFF .................................................................................................................................. 65
Contenidos
SCA06 | 5