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AVENTICS | SERCOS III | R412012610–BDL–001–AB
Appendix
Behavior after power on
13.3 Start-up behavior
After the assembly has been switched on (connecting the 24 V
logics supply), the hardware components are tested (start-up
test).
If the start-up test is successful and the bus voltage available,
the SERCOS III controller is initialized in accordance with the
presettings on the rotary switches and DIP switches.
After initialization, the module is in NRT mode until the master
establishes communication. It can now be powered up through
the various sequential phases until it reaches the operating
state "BB" (phase CP4). Acyclic process data exchange is
already possible in phases CP2/CP3 via the SVC channel.
13.4 SERCOS Device Description Markup
Language (SDDML)
The SDDML file is an ASCII file specified by SERCOS
International e.V. that describes the objects/performance data
for a SERCOS III device. This file exists for the bus coupler and
is called BDC-B-SER_32.XML.
The file can be downloaded from the Internet at
www.aventics.com/mediadirectory.