Ssi Interface; Principle - Balluff BTL5-S1 Serie Manual De Instrucciones

BTL5-S1 _ _ (B)-M _ _ _ _ -K(8)-SR32/SR115/K_ _/F_ _
Magnetostrictive Linear Position Sensor – Rod Style
6

SSI interface

6.1

Principle

SSI stands for Synchronous Serial Interface and describes
a digital synchronous interface with a differential clock line
and a differential data line.
With the first falling clock edge, the data word to be output
is buffered in the BTL to ensure data consistency. Data
output takes place with the first rising clock edge, i.e. the
BTL supplies a bit to the data line for each rising clock
edge. In doing so, the line capacities and delays of drivers
t when querying the data bits must be taken into account
v
in the controller.
Die max. clock frequency f depends on the cable length.
Clk
The t time, also called monoflop time, is started with the
m
last falling edge and is output as the low level with the last
rising edge. The data line remains at low until the t
has elapsed. Afterwards, the BTL is ready again to receive
the next clock package.
SSIn
T
Clk
Clk
1 2
Data
MSB
T
Clk
Clk
t
v
Data
Clk
Data
T = 1 / f SSI clock period, SSI clock frequency
Clk Clk
T = 1 / f Sampling period, sampling rate
A A
n Number of bits to be transmitted (requires n+1 clock impulses)
t = 31 ms Time until the SSI interface is ready again
m
t = 150 ns Transmission delay times (measured with a 1 m cable)
v
www.balluff.com
time
m
3 4 5 n
t
v
T
A
With the BTL5-S1_ _ B-..., position data is determined and
output in a timely manner and synchronous to the external
sampling period. For synchronous operation the sampling
period T must lie in the range T
A
switches to asynchronous operation outside of this range.
If the minimum sampling time is undercut, the BTL outputs
the same position value several times. The external
sampling rate is then greater than the internal rate. In
addition, T must be long enough so that the next clock
A
package does not occur in the t
package.
t
m
n+1
LSB
≤ T . The BTL
A, min A
range of the previous
m
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