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Idiomas disponibles
Idiomas disponibles
Execution Error Register
This register contains a number representing the last error encountered over the current interface.
The Execution Error Register is read and cleared using the 'EER?' command. On power up this
register is set to 0 for all interface instances.
Error messages have the following meaning:
0:
No error encountered
1-9:
Internal hardware error detected.
100:
Range error. The numeric value sent is not allowed. This includes numbers that are too
big or too small for the parameter being set and non-integers being sent where only
integers are allowed.
101:
A recall of set up data has been requested but the store specified contains corrupted
data. This indicates either a hardware fault or a temporary data corruption, which can be
corrected by writing data to the store again.
102:
A recall of set up data has been requested but the store specified does not contain any
data.
103:
Attempt to read or write a command on the second output when it is not available.
Typically this will occur if attempting to program the second output on single channel
instruments or on a two-channel instrument which is set to parallel mode.
104:
Command not valid with output on. For example, using the CONFIG <nrf> command to
change operating mode without first turning Output 2 off will cause error 104.
200:
Read Only: An attempt has been made to change the settings of the instrument from an
interface without write privileges, see the Interface Locking section.
Limit Event Status and Limit Event Status Enable Registers
For single output power supplies there is one Limit Event Status Register; for dual power supplies
(except if operating in parallel mode) there are two. These are read and cleared using 'LSR1?'
and 'LSR2?' respectively. On power-up these registers are set to 0 then immediately set to show
new limit status.
Any bits set in a Limit Event Status Register which correspond to bits set in the accompanying
Limit Event Status Enable Register will cause the LIM1 or LIM2 bit to be set in the Status Byte
Register.
Bit 7:
Reserved for future use
Bit 6:
Set when a trip has occurred that can only be reset from the front panel or by removing
and reapplying the AC power.
Bit 5:
Reserved for future use
Bit 4:
Set when output enters power limit (Unregulated mode).
Bit 3:
Set when an output over current trip has occurred
Bit 2:
Set when an output over voltage trip has occurred.
Bit 1:
Set when output enters current limit (CC mode)
Bit 0:
Set when output enters voltage limit (CV mode)
Status Byte Register and Service Request Enable Register
These two registers are implemented as required by the IEEE Std. 488.2.
Any bits set in the Status Byte Register which correspond to bits set in the Service Request Enable
Register will cause the RQS/MSS bit to be set in the Status Byte Register, thus generating a
Service Request on the bus.
The Status Byte Register is read either by the *STB? command, which will return MSS in bit 6, or
by a Serial Poll which will return RQS in bit 6. The Service Request Enable register is set by the
*SRE <nrf> command and read by the *SRE? command.
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