Tabla de contenido
INTEGRATED CIRCUITS BLOCK DIAGRAMS - SYNOPTIQUES INTERNES DES CIRCUITS INTEGRES -
SCHEMA A BLOCCHI DEL CIRCUITI INTEGRATI - VISTA INTERNA DE LOS CIRCUITOS INTEGRADOS
SMALL SIGNAL BOARD - PLATINE PETITS SIGNAUX - SIGNAL-PLATINE -
AGCOUT
SIF/AM
VP1
62
5
11
19
SW0
BUS
63
SIFIN1
SIF-
64
SIFIN2
AMPLIFIER
AGC
1
AGCSIF
3
IFIN2
2
IFIN1
VIF-
AMPLIFIER
22
SW1
BUS
AGCVIF
4
PLL-
DEMOD.
TOP
8
IFVCO2
AFC
7
IFVCO1
AGC/AFC
6
CONTROL
PLLIF
10
IFVO
VIDEO
MUTE
AMPLIFIER
MUTE
12
GDIN
GROUP
DELAY
GND1
9
CORR.
13
14
GDOUT
CVBSINT
CVBS/
Y4
INTEGRIERTE SCHALTUNGEN BLOCKSCHALTBILDER
PIASTRA PICCOLI SEGNALI - PLACA PEQUEÑA SEÑAL
VP2
DECDIG
DECBG
XTALA XTALB XTALC XTALD
35
45
33
54
55
SUPPLY
HUE
SYSTEM
IDENT
QSS MIXER
AM DEMODULATOR
FILTER
TUNING
CLOCHE
FILTER
IDENT
VIDEO
ACC
SWITCH
IDENT
34
17
16
23
24
AV2 CVBS1
CHRO
CVBS
MA4
TXT
GNDADC
VADC
21
20
26
YIN
24
UIN
ADC
22
VIN
Clamp
Timing
Generator
30
V50
31
H50
PD
N
27
28
32
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TACQ
CLKACQ
IC001 - TDA9321H
REFO
DET SECPLL
57
30
52
53
56
PAL/NTSC PLL
HUE CONTROL
PAL/NTSC
DEMOD.
PAL(NTSC)
SECAM
/ SECAM
DECODER
Fsc
SWITCH
BANDPASS
FILTER
Y-SWITCH
AUTO
HELPER
CHROMA
VIDEO SWITCH + CONTROL
21
18
15
26
20
AV1
CMB
CVBS/
CHRO
CVBS2
CVBS
Y3
MA3
IU308 - DMU0
SDA
SCL
Q11..0
WCTRL
RCTRL
12
3
68
1
5..9,
2,
63,
12..18
3,4
66,67
Memory Interf.
I2C
& time delay
Bus
compensation
Timing
Generator
PD
N
46
53
45
29
SEL
TDEFL
CLK DEFL
HDEFL VDEFL
PH1LF
SO
HACLP
VA
58
59
60
61
PULSE
VERTICAL
GENER.
DEVIDER
VCO
VERTICAL
+
SYNC
H-PLL
SEP.
R-Y
BASE-BAND
DELAY LINE
B-Y
VIDEO
SYNC
SEP.
IDENT
Y-DELAY
+
Y-DELAY
TRAPS
25
32
29
27
28
CMB
COMBY
CVBS
CMB
SYS2
SYS1
PIP
D11..0
GNDDAC VDAC
3
12
42
35,40
57..60,
47..52
36
37
DAC
41
10,,55,65
Timing
Generator
11,35,44
PD
N
43
56
TDISP
CLKDISP
SCL
AS
SDA
48
46
47
I2C-BUS
TRANSCEIVER
49
YO
U
50
Y / U / V
UO
SWITCH
V
51
VO
36
RI1
RGB-
37
GI1
MATRIX
38
BI1
39
RGBIN1
41
RI2
42
GI2
43
BI2
40
RGBIN2
44
31
COMBC
GND2
GND3
YOUT
UOUT
VOUT
VCC
GND
Tabla de contenido
