THOMSON DPL950VD Manual Del Usuario página 4

MPEG BOARD SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE MPEG - SCHALTBILD MPEG - SCHEMA DELLA PIASTRA MPEG - ESQUEMA DE LA PLATINA MPEG (2/3)
NVERR
RERR
SCART_CNTL1_OUT
SCART_CNTL2_OUT
V_MUX_CNTL1_OUT
V_MUX_CNTL2_OUT
V_MUX_CNTL3_OUT
A_IN_MUX_CNTL1_OUT
A_IN_MUX_CNTL2_OUT
+5VD_FRONT
CON14
DOOR_M+
DOOR_M-
DOOR_SNS_OPEN
DOOR_SNS_CLS
RMC
KEY_SCAN (1:7)
FRONT_DGND
RMC
+5VD_FRONT
LED_STANDBY
KEY_SCAN1
KEY_SCAN1
KEY_SCAN2
CCLK_FPGA
KEY_SCAN2
KEY_SCAN3
KEY_SCAN3
DAT_FPGA
KEY_SCAN4
KEY_SCAN4
KEY_SCAN5
KEY_SCAN5
C197
100nF
KEY_SCAN_IN1
C198
220uF
CON7
+5VD_FRONT
VFD_KEY_IN
VFD_DAT_OUT
R221
100
VFD_DAT_IN
100
VFD_CLK
100
VFD_CS
KEY_SCAN1
100
KEY_SCAN1
KEY_SCAN2
KEY_SCAN2
KEY_SCAN7
CON10
KEY_SCAN3
KEY_SCAN3
KEY_SCAN4
KEY_SCAN4
KEY_SCAN5
KEY_SCAN5
KEY_SCAN6
KEY_SCAN6
KEY_SCAN7
KEY_SCAN6
KEY_SCAN7
KEY_SCAN_IN1
KEY_SCAN_IN2
CON2
LED_STANDBY
FRONT_DGND
-27V
-27V
VF1
VF1
VF2
VF2
CHGND
TOUCH_KEY
CON12
ENCODER_A
ENCODER_B
FRONT_DGND
+5VD_FRONT
KEY_SCAN1
KEY_SCAN1
KEY_SCAN2
KEY_SCAN2
KEY_SCAN3
KEY_SCAN3
KEY_SCAN4
KEY_SCAN4
KEY_SCAN5
KEY_SCAN5
KEY_SCAN_IN2
C98
100P
C99
100P
IN4148
D30
TO FRONT BOARD
D31
IN4148
RTDVD101 ONLY
CHGND
FRONT_DGND
MDGND
+5VD
+5VD_AUD
C132
C131
100nF
C134
100nF
3.3uF
3.3uF
C133
8415_DGND
R189
33
I2C_CLK
U27
R190
28
1
33
SDL
SDA
I2C_DAT
27
2
AD1
AD0
R188
47K
26
3
RXP6
AD2
25
4
RXP5
RXP
SPDIF_IN
24
5
C119
10nF
S H/
RXN
C31
10nF
23
6
VL+
VA+
10uF
C118
13.5M
22
7
DGND
AGND
C124
21
8
CMCK
FILT
8415_DGND
20
9
10nF
U
RST
19
10
INT
RMCK
R185
18
11
SDOUT
RERR
33R
R186
17
12
OLRCK
RXP1
33R
R187
16
13
OSCLK
RXP2
33R
15
14
RXP4
RXP3
8415_DGND
DIGITAL_A_IN_MUX
R191
CS8415A
33
SUB_RST
R194
33
DGND
R280
33R
R279
33R
R218
R219
R220
10k
Q19
3
KRA102S
EMIT
DGND
BASE
1
COL
2
Q18
+5VD
DTC323
FRONT_DGND
DGND
Q16
Q5
Q6
Q17
DTC323
DTC323
R75
DTC323
DTC323
R76
10K
10K
FRONT_DGND
5
+3.3V
C79
10nF
Q15
10uF
C78
DTC3233
MDGND
U30
1
20
OE1
Vcc
2
19
I0
OE2
33R
R24
3
18
O4
O0
4
17
I1
I4
33R
5
16
R31
O5
O1
6
15
I2
I5
CS5333_DATA
R46
7
14
O6
O2
8
13
33R
I3
I6
DA_BCK
9
12
O7
O3
10
11
GND
I7
DA_LRCK
GPIO(01:08)
+5VD
10nF
C82
10uF
C83
U6
20
1
VCC
OE
IN245G
GPIO01
19
2
V0
D0
DOOR_SNS_OPEN
18
3
GPIO02
O1
D1
17
4
GPIO03
DOOR_SNS_CLS
O2
D2
HEADPHONE_DET
16
5
GPIO04
O3
D3
AMP_POW_FAIL
GPIO05
15
6
O4
D4
TRAY_SENSE
14
7
GPIO06
O5
D5
13
8
GPIO07
O6
D6
12
9
GPIO08
O7
D7
TUNED
11
10
CP
GND
DGND
TRAY_SENSE
10k
R84
RA05
10k
OUT245G
+5VD
U16
C80
20
1
VCC
OE
19
2
10nF
GPIO01
V0
D0
PLL_CE
18
3
GPIO02
O1
D1
SERIAL_CLK
GPIO03
17
4
O2
D2
SERIAL_DAT
16
5
GPIO04
O3
D3
15
6
GPIO05
O4
D4
VFD_DRV_CS_OUT
14
7
GPIO06
O5
D5
GPIO07
PROG_FPGA
13
8
O6
D6
DAMP_RST
12
9
GPIO08
O7
D7
11
10
CP
GND
SUB_RST
10k
R85
100nF
C109
C195
U12
1nF
+5VD
20
1
VCC
OE
SCART_CNTL1_OUT
19
2
GPIO01
V0
D0
SCART_CNTL2_OUT
18
3
GPIO02
O1
D1
V_MUX_CNTL1_OUT
GPIO03
17
4
O2
D2
V_MUX_CNTL2_OUT
16
5
GPIO04
O3
D3
V_MUX_CNTL3_OUT
15
6
GPIO05
O4
D4
A_IN_MUX_CNTL1_OUT
14
7
GPIO06
O5
D5
A_IN_MUX_CNTL2_OUT
GPIO07
13
8
O6
D6
12
9
GPIO08
O7
D7
R69
11
10
CP
GND
C205
470uF
MUTE_DMIX
C193
R314
MDGND
1k
1nF
100nF
C110
U11
+5VD
20
1
VCC
OE
MUTE_PHONE
GPIO01
19
2
V0
D0
PD1_DAMP
18
3
GPIO02
O1
D1
PD2_DAMP
17
4
GPIO03
O2
D2
P_CON
GPIO04
16
5
O3
D3
DOOR_IN
GPIO05
15
6
O4
D4
DOOR_OUT
14
7
GPIO06
O5
D5
TRAY_IN
13
8
GPIO07
O6
D6
TRAY_OUT
GPIO08
12
9
O7
D7
11
10
CP
GND
C194
R315
1nF
1k
TO TUNER BD
13
12
11
10
9
8
7
6
5
4
3
2
1
CON3
IN_LRCK
IN_BCK
IN_DATA
10uH
C159
C160
100nF
100uF
AGND
+5VD
L_+12VM
22UH
C115
100uF
DGND
R165
IN4148
C114
D20
47K
1.8K
10uF
R174
R166
KTA1504
5.6K
Q4
10K
R65
TRAY_SENSE
10K
D18
Q3
R64
RB501V-40
L_MGND
R68
10K
KTC3875
R61
5.6K
IN245G
R62
1N4148
R63
C112
68K
OUT245G
D19
100K
1uF
OUT574CK1
OUT574CK2
OUT574OE
L_MGND
+9VM
22UH
C116
C135
+5VD
100nF
100uF
DGND
R197
R198
1K
1K
10nF
10nF
C145
C123
C196
100nF
D32
IN4148
D33
IN4148
DGND
CHGND
6
+12V_AUD
L3
MOTOR CONTROL UNIT
TRAY_M-
470
TRAY_M+
R66
10nF
C113
L_MGND
470
R67
D21
5.6V
L_MGND
DGND
470
R245
C117
100nF
L_MGND
470
5.6V
R246
D12
DGND
L_MGND
ASMP1002
First issue 01 / 04
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