LG FA162 Manual De Servicio página 25

8. PS9829B
• CONFIGURACIÓN DEL PIN
OVERLOAD
EPD_ENA
SO/SDA
SCK/SCL
DVDD
DVSS
SI/I2C_AD0
/CS/I2C_AD2
SPI/I2C
IO_VSS
CLK_IN
IO_VDD
DMIX_LRCK
DMIX_BCK
DMIX_SDOUT
DVDD
DVSS
DMIX_MCLK
IO_VDD
IO_VSS
/RESET
TEST_MODE1
TEST_MODE2
SCAN_ENA
TEST_MODE3
• DIAGRAMA DE BLOQUE
MBCK
MLRCK
Input
MSDIN[0:3]
&
Output
SBCK
MUX
SLRCK
SSDIN[0:3]
Sample
Rate
Converter
Input
Mapper
MIC_MCLK
Mic.
MIC_BCK
Input
MIC_LRCK
Processor
MIC_SDIN
SPI/I2C
SO/SDA
Host
SCK/SCL
Interface
SI/I2C_AD0
2
(I C, SPI)
/CS/I2C_AD2
EXT_MUTE
PULSUS
PS9829B
Down
Mixer
4 Band
Mixer
EQ
Internal Clock
Reset & Power Down
Internal Controls
PLL
50 IO_VSS
49 PWM1_P
48 PWM1_M
47 IO_VDD
46 PWM_HP_L_P
45 PWM_HP_L_M
44 IO_VSS
43 DVSS
42 DVDD
41 PWM_HP_R_P
40 PWM_HP_R_M
39 IO_VDD
38 IO_VSS
37 PWM_SWL_P
36 PWM_SWL_M
35 DVSS
34 DVDD
33 MIC_SDIN
32 MIC_LRCK
31 MIC_BCK
30 MIC_MCLK
29 IO_VDD
28 IO_VSS
27 EXT_MUTE
26 SSDIN3
Serial Audio
Output
interface
Automatic
Gain
Limiter
Bass Main Trim
Manager Volume Volume
Internal Reset
Power Supply
3-14
DMIX_MCLK
Serial
OLRCK
Audio
OBCK
Output
DMIX_SDOUT
interface
PWM1_P/M
PWM2_P/M
PWM3_P/M
PWM4_P/M
PWM5_P/M
PWM6_P/M
PWM7_P/M
PWM
PWM8_P/M
Modulator
PWM_HP_L_P/M
PWM_HP_R_P/M
PWM_SWL_P/M
POP
EPD_ENA
NR
OVERLOAD