Limit Event Status And Limit Event Status Enable Registers; Status Byte Register And Service Request Enable Register - Metek Sorensen XEL serie Manual De Operación

103: Attempt to read or write a command on the second output when it is not available.
Typically this will occur if attempting to program the second output on single channel
instruments or on a two-channel instrument which is set to parallel mode.
104: Command not valid with output on. This is typically caused by using the 'IRANGE <n>'
command without first turning the output off.
200: Read Only: An attempt has been made to change the settings of the instrument from an
interface without write privileges, see the Interface Locking section.

Limit Event Status and Limit Event Status Enable Registers

For single output power supplies there is one Limit Event Status Register; for dual power supplies
(except if operating in parallel mode) there are two. These are read and cleared using 'LSR1?' and
'LSR2?' respectively. On power-up these registers are set to 0 then immediately set to show new
limit status.
Any bits set in a Limit Event Status Register which correspond to bits set in the accompanying Limit
Event Status Enable Register will cause the LIM1 or LIM2 bit to be set in the Status Byte Register.
Bit 7: Reserved for future use
Bit 6: Set when a trip has occurred that can only be reset from the front panel or by removing
and reapplying the AC power.
Bit 5: Reserved for future use
Bit 4: Reserved for future use
Bit 3: Set when an output over current trip has occurred
Bit 2: Set when an output over voltage trip has occurred.
Bit 1: Set when output enters current limit (CC mode)
Bit 0: Set when output enters voltage limit (CV mode)

Status Byte Register and Service Request Enable Register

These two registers are implemented as required by the IEEE Std. 488.2.
Any bits set in the Status Byte Register which correspond to bits set in the Service Request Enable
Register will cause the RQS/MSS bit to be set in the Status Byte Register, thus generating a Service
Request on the bus.
The Status Byte Register is read either by the *STB? command, which will return MSS in bit 6, or by
a Serial Poll which will return RQS in bit 6. The Service Request Enable register is set by the *SRE
<nrf> command and read by the *SRE? command.
Bit 7 - Not used.
Bit 6 - RQS/MSS. This bit, as defined by IEEE Std. 488.2, contains both the Requesting Service
message and the Master Status Summary message. RQS is returned in response to a
Serial Poll and MSS is returned in response to the *STB? command.
Bit 5 - ESB. The Event Status Bit. This bit is set if any bits set in the Standard Event Status
Register correspond to bits set in the Standard Event Status Enable Register.
Bit 4 - MAV. The Message Available Bit. This will be set when the instrument has a response
message formatted and ready to send to the controller. The bit will be cleared after the
Response Message Terminator has been sent.
Bit 3 - Not used.
Bit 2 - Not used.
Bit 1 - LIM2. This will be set if any bits in Limit Event Status Register 2 are set and
corresponding bits are set in Limit Event Status Enable Register 2.
Bit 0 - LIM1. This will be set if any bits in Limit Event Status Register 1 are set and
corresponding bits are set in Limit Event Status Enable Register 1.
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