1
VCC
VCC
A
R1
R2
4K7
4K7
C2
C3
100nF
100nF
B
R13
1K
Out_sw0
R7
330R
Out_sw1
R8
330R
D4
Out_sw2
1N4148
R10
330R
CN2
R11
10K
1
R12
82R
2
L1
3
C
4
Out_sw1
5
Out_sw2
6
In_sw0
7
In_sw1
8
Header 8H
D
1
2
U1
In_sw0
6
RB0/INT
Rx
7
RB1/RX/DT
Tx
8
RB2/TX/CK
In_sw1
9
RB3/CCP1
10
RB4/PGM
11
RB5
PGC
12
RB6/T1OSO/T1CKI/PGC
PGD
13
RB7/T1OSI/PGD
VCC
14
VDD
C4
D5
100nF
PIC16F627-20/SO
SMAJ5.0
Rx
VCC
Tx
100uH
2
3
17
RA0/AN0
18
RA1/AN1
1
RA2/AN2/VREF
2
RA3/AN3/CMP1
3
RA4/T0CKI/CMP2
4
Prog
RA5/MCLR/VPP
15
RA6/OSC2/CLKOUT
16
RA7/OSC1/CLKIN
5
Y1
VSS
3.6864MHz
C5
C6
15pF
15pF
VCC
CN3
1
PGC
2
PGD
3
Prog
4
5
Programação
3
R6
D3
180R
C1
1N4148
100nF
VCC
VCC
VCC
C8
D6
100uF
SMAJ5.0
Title
Size
Number
A4
Date:
5/8/2008
File:
C:\projetos\..\PACTRL_CM12.SCHDOC Drawn By:
4
A
CN1
R3
330R
1
R 4
330R
2
R5
330R
3
4
5
Out_sw0
6
In_sw0
7
In_sw1
8
Header 8H
B
C
C7
100nF
D
Revision
Sheet of
4